W9425G6EH
6. BLOCK DIAGRAM
CLK
CLK
DLL
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
CAS
COMMAND
DECODER
GENERATOR
WE
A10
COLUMN DECODER
CELL ARRAY
BANK #0
COLUMN DECODER
CELL ARRAY
BANK #1
A0
A9
A11
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A12
BA0
BA1
PREFETCH REGISTER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
COLUMN
COUNTER
LDQS
UDQS
LDM
UDM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
CELL ARRAY
BANK #2
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 8192 * 512 * 16
Publication Release Date:Dec. 03, 2008
-8-
Revision A08
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